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ASAHI KASEI [AKD4562] AKD4562 Evaluation board Rev.A for AK4562 GENERAL DESCRIPTION AKD4562 is an evaluation board for the portable digital audio 20bit A/D and D/A converter, AK4562. The AKD4562 can evaluate A/D converter D/A converter separately in addition to loopback mode (A/D D/A). The A/D section can be evaluated by interfacing with AKM's DAC evaluation boards directly. The AKD4562 has the interface with AKM's wave generator using ROM data and AKM's ADC evaluation boards. Therefore, it's easy to evaluate the D/A section. The AKD4562 also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector. n Ordering guide AKD4562 --Evaluation board for AK4562 (Cable for connecting with printer port of IBM-AT, compatible PC and control software are packed with this.) FUNCTION * Compatible with 2 types of interface - Direct interface with AKM's A/D & D/A converter evaluation boards - DIT/DIR with optical input/output * BNC connector for an external clock input * 10pin Header for serial control mode VA GND VT LIN1/2 RIN1/2 AK4562 LOUT1/2 ROUT1/2 CS8412 (DIR) Opt In AK4353 (DIT) Opt Out Control Data 10pin Header Clock Generator A/D, D/A Data ROM Data 10pin Header Figure 1. AKD4562 Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual. '00/06 ASAHI KASEI [AKD4562] 1. Evaluation Board Manual n Input / Output circuits & Set-up jumper pin for Input / Output circuits (1) LINE Block (a) LIN1,2/RIN1,2 Input circuits J2 LIN C38 10u + LIN LIN1 LIN1 LIN2 LIN2 JP15 R36 560 J4 RIN C41 10u + JP18 RIN1 RIN1 RIN2 RIN2 R38 560 RIN Figure 2. LIN1,2/RIN1,2 Input circuits 1. Analog signal is input to LIN1 and RIN1 pins via J2 and J4 connectors. JP15 LIN LIN1 LIN2 JP18 RIN RIN1 RIN2 2. Analog signal is input to LIN2 and RIN2 pins via J2 and J4 connectors. JP15 LIN LIN1 LIN2 JP18 RIN RIN1 RIN2 '00/06 ASAHI KASEI [AKD4562] (b) LOUT1/ROUT1 and OPGAL/OPGAR Selection circuits R34 220 LOUT1 LOUT1 C39 1u C37 22u R35 10k JP16 LIO OPGL + J3 LOUT1 LOUT1 OPGAL OPGL JP17 OPGL + C40 1u + R37 560 R39 220 ROUT1 ROUT1 C43 1u C42 22u R40 10k JP19 RIO + + ROUT1 OPGAR OPGR JP20 OPGR + J5 ROUT1 C44 1u Figure 3. LOUT1/ROUT1 and OPGAL/OPGAR Selection circuits 1. Analog signal is input to OPGAL and OPGAR pins via J3 and J5 connectors. JP16 LIO JP17 OPGL JP19 RIO JP20 OPGR LOUT1 OPGL LOUT1 OPGL ROUT1 OPGR ROUT1 OPGR R41 560 OPGR 2. Analog signal is output to LOUT1 and ROUT1 pins via J3 and J5 connectors. JP16 LIO JP17 OPGL JP19 RIO JP20 OPGR LOUT1 OPGL LOUT1 OPGL ROUT1 OPGR ROUT1 OPGR 3. Analog signal is input to OPGAL and OPGAR pins via LOUT1 and ROUT1 pins. JP16 LIO JP17 OPGL JP19 RIO JP20 OPGR LOUT1 OPGL LOUT1 OPGL ROUT1 OPGR ROUT1 OPGR '00/06 ASAHI KASEI [AKD4562] (2) Other Jumper pins 1. JP1 (CSN) : Selection of CSN pin SSB : SSB mode. AKM : AKM mode. 2. JP2 (SSB) : Selection of SSB mode or AKM mode OPEN : AKM mode. SHORT : SSB mode. 3. JP3 (TST) : Selection of TEST pin OPEN : Normal mode. SHORT : Test mode. * Always open. 4. JP4 (GND) : Analog ground and Digital ground OPEN : Separated. SHORT : Common. (The connector "DGND" can be open.) * AKM assumes no responsibility for the trouble when using the above circuit examples. n Operation sequence 1) Set up the power supply lines. [VA] (orange) = 2.2 3.0V [VT] (orange) = 1.8 3.0V [D2V] (orange) = 1.8 3.0V [D5V] (red) = 3.6 5.0V [AGND] (black) = 0V [DGND] (black) = 0V : for VA of AK4562 (typ. 2.5V) : for VT of AK4562 (typ. 2.5V) : for 74LVC541 (typ. 2.5V) : for logic (typ. 5.0V) : for analog ground : for logic ground Each supply line should be distributed from the power supply unit. VT and D2V must be same voltage level. 2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.) Note : This evaluation board corresponds to I2S compatible mode for evaluation of A/D. 3) Power on. The AK4562 and AK4353 should be reset once bringing SW1, 2 "L" upon power-up. '00/06 ASAHI KASEI [AKD4562] n Evaluation mode Applicable Evaluation Mode 1) Evaluation of loopback mode (default) 2) Evaluation of D/A using ideal sine wave generated by ROM data 3) Evaluation of D/A using A/D converted data 4) Evaluation of D/A using DIR (Optical Link) 5) Evaluation of A/D using D/A converted data 6) Evaluation of A/D using DIT (Optical Link) 7) All interface signals including master clock are fed externally. 6) AKD43XX 5) D/A Board AKD4562 PORT2 10pin-Header 1) PORT4 DIR PORT1 DIT PORT3 10pin-Header CD Player 4) AKD53XX A/D Board 2) 3) ROM Board 1) Evaluation of loopback mode. 32fs 64fs ADC DIR ADC DIR ADC DIR VD GND EXT XTL DIR '00/06 ASAHI KASEI [AKD4562] 2) Evaluation of D/A using A/D converted data from ideal sine wave generated by ROM data. Digital signals generated by AKD43XX are used. PORT3 is used for the interface with AKD43XX. Master clock is sent from AKD4562 to AKD43XX and BCLK, LRCK, SDTI are sent from AKD43XX to AKD4562. Nothing should be connected to PORT4. In case of using external clock through a BNC connector (J1), select EXT on JP13 (CLK) and short JP14 (XTE). JP6 X_BCLK JP7 LRCK JP8 BCLK JP11 SDTI JP12 DIR JP13 CLK JP14 XTE 32fs 64fs ADC DIR ADC DIR ADC DIR VD GND EXT XTL JP14 XTE XTL JP14 XTE XTL DIR 3) Evaluation of D/A using A/D converted data. It is possible to make evaluation in the form of analog inputs and analog outputs by interfacing with various AKM's A/D evaluation boards with PORT3. Nothing should be connected to PORT4. In case of using external clock through a BNC connector (J1), select EXT on JP13 (CLK) and short JP14 (XTE). JP6 X_BCLK JP7 LRCK JP8 BCLK JP11 SDTI JP12 DIR JP13 CLK 32fs 64fs ADC DIR ADC DIR ADC DIR VD GND EXT EXT DIR 4) Evaluation of D/A using DIR. (Optical link) PORT4 (DIR) is used. DIR generates MCLK, BCLK, LRCK and SDATA from the received data through optical connector (TORX176). Used for the evaluation using CD test disk. Nothing should be connected to PORT3. DIR (CS8412) corresponds to only I2S compatible mode or 16 bit LSB justified. JP6 X_BCLK JP7 LRCK JP8 BCLK JP11 SDTI JP12 DIR JP13 CLK 32fs 64fs ADC DIR ADC DIR ADC DIR VD GND DIR '00/06 ASAHI KASEI [AKD4562] 5) Evaluation of A/D using D/A converted data. It is possible to make evaluation in the form of analog inputs and analog outputs by interfacing with various AKM's D/A evaluation boards with PORT3. Nothing should be connected to PORT4. JP6 X_BCLK JP7 LRCK JP8 BCLK JP11 SDTI JP12 DIR JP13 CLK JP14 XTE 32fs 64fs ADC DIR ADC DIR ADC DIR VD GND EXT XTL JP14 XTE XTL JP14 XTE XTL DIR 6) Evaluation of A/D using DIT. (Optical link) PORT1 (DIT) is used. DIT generates audio bi-phase signal from received data and which is output through optical connector (TOTX176). It is possible to connect AKM's D/A converter evaluation boards on the digital-amplifier which equips DIR input. Nothing should be connected PORT3 and PORT4. In case of using external clock through a BNC connector (J1), select EXT on JP13 (CLK) and short JP14 (XTE). DIT (AK4353) corresponds to only I2S compatible mode. JP6 X_BCLK JP7 LRCK JP8 BCLK JP11 SDTI JP12 DIR JP13 CLK 32fs 64fs ADC DIR ADC DIR ADC DIR VD GND EXT EXT DIR 7) All interfacing signals (MCLK, BCLK, LRCK) are fed from the external circuit through PORT3. PORT3 is used. JP7, 8, 11 and 13 should be open. JP6 X_BCLK JP7 LRCK JP8 BCLK JP11 SDTI JP12 DIR JP13 CLK 32fs 64fs ADC DIR ADC DIR ADC DIR VD GND DIR n The function of the toggle SW Upper-side is "H" and lower-side is "L". [SW1] (PDN): Power down of AK4562. Keep "H" during normal operation. [SW2] (DIT): Power down of AK4353. Keep "H" during normal operation. n Indication for LED [LED1] (VERF): Monitor VERF pin of the CS8412. LED turns on when some error has occurred to CS8412. [LED2] (PREM): Indicate whether the input data of CS8412 is pre-emphasized or not. '00/06 ASAHI KASEI [AKD4562] n Serial Control The AK4562 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT2 (CTRL) with PC by 10 wire flat cable packed with the AKD4562. Connect PC CSN CCLK CDTI AKD4562 10 wire flat cable 10pin Connector 10pin Header Figure 4. Connect of 10 wire flat cable '00/06 ASAHI KASEI [AKD4562] 2. Control Software Manual n Set-up of evaluation board and control software 1. Set up the AKD4562 according to previous term. 2. Connect IBM-AT compatible PC with AKD4562 by 10-line type flat cable (packed with AKD4562). Take care of the direction of 10pin header. (This control software does not operate on Windows NT, therefore please operate it on Windows95/98.) 3. Insert the floppy-disk labeled "AKD4562 Control Program ver 1.0" into the floppy-disk drive. 4. Access the floppy-disk drive and double-click the icon of "AKD4562.exe" to set up the control program. This software corresponds to only AKM mode. 5. Then please evaluate according to the follows. n Explanation of each buttons 1. [Port Setup] : 2. [Reset] : 3. [Function1] : 4. [Function2] : 5. [Write] : Set up the printer port. Initialize the register of AK4562. Dialog to write data by keyboard operation. Dialog to evaluate IPGA and OPGA. Dialog to write data by mouse operation. Note : AK4353(DIT) is fixed to MCLK=256fs and I2S compatible mode. Therefore, in the case of evaluation for AK4562's ADC, it is necessary for AK4562 to set up MCLK=256fs and I2S compatible mode. n Explanation of each dialog 1. [Function1 Dialog] : Address Box: Data Box: Dialog to write data by keyboard operation Input register address in 2 figures of hexadecimal. Input register data in 2 figures of hexadecimal. If you want to write the input data to AK4562, click "OK" button. If not, click "Cancel" button. '00/06 ASAHI KASEI [AKD4562] 2. [Function2 Dialog] : Dialog to evaluate IPGA and OPGA This dialog corresponds to only addr=03H and 04H. Address Box: Input register address in 2 figures of hexadecimal. Start Data Box: Input start data in 2 figures of hexadecimal. End Data Box: Input end data in 2 figures of hexadecimal. Interval Box: Data is written to AK4562 by this interval. Step Box: Data changes by this step. Mode Select Box: If you check this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 If you do not check this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 If you want to write the input data to AK4562, click "OK" button. If not, click "Cancel" button. 3. [Write Dialog] : Dialog to write data by mouse operation There are dialogs corresponding to each register. Click the "Write" button corresponding to each register to set up the dialog. If you check the check box, data becomes "H" or "1". If not, "L" or "0". If you want to write the input data to AK4562, click "OK" button. If not, click "Cancel" button. n Operation flow Keep the following flow surely. 1. Set up the control program according to explanation above. 2. Click "Port Setup" button. 3. Click "Write default" button. 4. Then set up the dialog and input data. n Indication of data Input data is indicated on the register map. Red letter indicates "H" or "1" and blue one indicates "L" or "0". Blank is the part that is not defined in the datasheet. n Attention on the operation If you set up Function1 or Function2 dialog, input data to all boxes. Attention dialog is indicated if you input data or address that is not specified in the datasheet or you click "OK" button before you input data. In that case set up the dialog and input data once more again. These operations does not need if you click "Cancel" button or check the check box. '00/06 ASAHI KASEI [AKD4562] MEASUREMENT RESULTS [Measurement condition] * Measurement unit : Audio Precision, System Two * MCLK : 256fs * BCLK : 64fs * fs : 44.1kHz * Bit : 20bit * Power Supply : VA=VD=VT=2.5V * Interface : DIR/DIT * Temperature : Room [Measurement Results] Parameter ADC Analog Input Characteristics S/(N+D) (-0.5dB Input) D-Range S/N Interchannel Isolation DAC Analog Output Characteristics S/(N+D) D-Range (A-weighted) S/N (A-weighted) Interchannel Isolation Output PGA Characteristics (OPGA) S/(N+D) S/N (A-weighted) Noise level at Mute (A-weighted) (A-weighted) (A-weighted) Input pin LIN1 / RIN1 LIN2 / RIN2 LIN1 / RIN1 LIN2 / RIN2 LIN1 / RIN1 LIN2 / RIN2 LIN1 / RIN1 LIN2 / RIN2 OPGAL / OPGAR OPGAL / OPGAR OPGAL / OPGAR Results (Lch / Rch) 85.3 / 84.8 85.4 / 84.7 88.6 / 88.6 88.6 / 88.6 88.6 / 88.6 88.6 / 88.6 109.6 / 108.7 109.7 / 109.8 89.5 / 89.5 93.0 / 93.0 93.2 / 93.2 109.5 / 108.7 91.7 / 91.7 94.2 / 94.2 108.5 / 108.6 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB '00/06 ASAHI KASEI [AKD4562] [ADC Plot] AKM A K 4 5 6 2 T HD+N vs. Input Level VA=VD=VT=2.5V, fs=44.1kHz, fin=1kHz -70 -73 -76 -79 d B F S -82 -85 -88 -91 -94 -97 -100 -120 -110 -100 -90 -80 -70 -60 dBr -50 -40 -30 -20 -10 Figure 1. THD+N vs. Input Level AKM A K 4 5 6 2 T HD+N vs. Input Frequency VA=VD=VT=2.5V, fs=44.1kHz, Input=-0.5dBr -70 -73 -76 -79 d B F S -82 -85 -88 -91 -94 -97 -100 20 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 2. THD+N vs. Input Frequency '00/06 ASAHI KASEI [AKD4562] AKM A K 4 5 6 2 L inearity VA=VD=VT=2.5V, fs=44.1kHz, fin=1kHz +0 -20 -40 d B F S -60 -80 -100 -120 -120 -110 -100 -90 -80 -70 -60 dBr -50 -40 -30 -20 -10 +0 Figure 3. Linearity AKM A K 4 5 6 2 F requency Response VA=VD=VT=2.5V, fs=44.1kHz, Input=-0.5dBr +0 -0.2 -0.4 -0.6 d B F S -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 20 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 4. Frequency Response '00/06 ASAHI KASEI [AKD4562] AKM A K 4 5 6 2 C rosstalk VA=VD=VT=2.5V, fs=44.1kHz, Input=-0.5dBr -90 -95 -100 -105 d B -110 -115 -120 -125 -130 20 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 5. Crosstalk AKM A K 4 5 6 2 F F T P lot VA=VD=VT=2.5V, fs=44.1kHz, Input=-0.5dBr, fin=1kHz +0 -20 -40 -60 d B F S -80 -100 -120 -140 -160 20 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 6. FFT Plot '00/06 ASAHI KASEI [AKD4562] AKM A K 4 5 6 2 F F T P lot VA=VD=VT=2.5V, fs=44.1kHz, Input=-60dBr, fin=1kHz +0 -20 -40 -60 d B F S -80 -100 -120 -140 -160 20 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 7. FFT Plot AKM A K 4 5 6 2 F F T P lot VA=VD=VT=2.5V, fs=44.1kHz, fin=None +0 -20 -40 -60 d B F S -80 -100 -120 -140 -160 20 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 8. FFT Plot '00/06 ASAHI KASEI [AKD4562] [DAC Plot] AKM A K 4 5 6 2 T HD+N vs. Input Level VA=VD=VT=2.5V, fs=44.1kHz, fin=1kHz -70 -73 -76 -79 d B r A -82 -85 -88 -91 -94 -97 -100 -120 -110 -100 -90 -80 -70 -60 dBFS -50 -40 -30 -20 -10 +0 Figure 1. THD+N vs. Input Level AKM A K 4 5 6 2 T HD+N vs. Input Frequency VA=VD=VT=2.5V, fs=44.1kHz, Input=0dBFS -80 -82 -84 -86 d B r A -88 -90 -92 -94 -96 -98 -100 20 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 2. THD+N vs. Input Frequency '00/06 ASAHI KASEI [AKD4562] AKM A K 4 5 6 2 L inearity VA=VD=VT=2.5V, fs=44.1kHz, fin=1kHz +0 -20 -40 d B r A -80 -60 -100 -120 -120 -110 -100 -90 -80 -70 -60 dBFS -50 -40 -30 -20 -10 +0 Figure 3. Linearity AKM A K 4 5 6 2 F requency Response VA=VD=VT=2.5V, fs=44.1kHz, Input=0dBFS +0.5 +0.4 +0.3 +0.2 d B r A +0.1 +0 -0.1 -0.2 -0.3 -0.4 -0.5 2k 4k 6k 8k 10k Hz 12k 14k 16k 18k 20k Figure 4. Frequency Response '00/06 ASAHI KASEI [AKD4562] AKM A K 4 5 6 2 C rosstalk VA=VD=VT=2.5V, fs=44.1kHz, Input=0dBFS -80 -85 -90 -95 -100 d B -105 -110 -115 -120 -125 -130 20 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 5. Crosstalk AKM A K 4 5 6 2 F F T P lot VA=VD=VT=2.5V, fs=44.1kHz, Input=0dBFS, fin=1kHz +0 -20 -40 d B r A -60 -80 -100 -120 -140 -160 20 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 6. FFT Plot '00/06 ASAHI KASEI [AKD4562] AKM A K 4 5 6 2 F F T P lot VA=VD=VT=2.5V, fs=44.1kHz, Input=-60dBFS, fin=1kHz +0 -20 -40 d B r A -60 -80 -100 -120 -140 -160 20 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 7. FFT Plot AKM A K 4 5 6 2 F F T P lot VA=VD=VT=2.5V, fs=44.1kHz, fin=None +0 -20 -40 d B r A -60 -80 -100 -120 -140 -160 20 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 8. FFT Plot '00/06 A B C D E CN1 52 51 50 49 48 47 46 45 44 43 42 41 40 E E R1 51 CN2 CN3 1 D 39 D 28 27 26 25 24 23 22 2 U1 38 PDN OPGAL LOUT1 CSN SSB ROUT1 CCLK R2 51 37 CDTI 21 3 1 4 2 5 3 6 4 C OPGAR R3 51 36 LOUT2 LRCK 20 35 ROUT2 MCLK 19 R4 51 34 LIN1 7 5 8 6 9 7 10 VCOM RIN2 LIN2 RIN1 AK4562 TST 18 R5 51 33 C BCLK 17 32 SDTI 16 R6 51 31 SDTO DGND AGND VREF 15 R7 51 30 VD VA VT R8 51 29 11 10 11 12 13 14 8 9 12 B 28 B 13 27 C1 0.1u C4 2.2u + C5 0.1u C2 0.1u C3 0.1u + C6 10u + R9 10 C8 10u + C7 10u A CN4 14 15 16 17 18 19 20 21 22 23 24 25 26 A Title Size Document Number AKD4562 AK4562 Sub 1 of Rev A3 Date: A B C D A 1 Wednesday, February 02, 2000 Sheet E A B C D E OPGAR OPGAL ROUT1 VT LOUT1 D2V SSB JP1 CSN CSN CSN1 R1 51 AKM JP2 SSB E JP4 GND DGND AGND SSB open = "L" short = "H" SSB R2 47k JP3 TST open = "L" short = "H" TST R3 47k E 52 51 50 49 48 47 46 45 44 43 42 41 U1 40 OPGAR ROUT1 PDN OPGAL CSN NC NC NC NC NC LOUT1 1 SSB NC U2 NC NC 39 11 Y8 A8 9 PDN 2 D NC NC 38 12 Y7 A7 8 CSN D R4 LOUT2 3 LOUT2 CCLK 37 51 13 Y6 A6 7 CCLK R5 ROUT2 4 ROUT2 CDTI 36 51 14 Y5 A5 6 CDTI 5 NC NC 35 15 Y4 A4 5 LRCK R6 6 NC 51 16 Y3 A3 4 LIN1 7 LIN1 AK4562 LRCK 34 MCLK R7 MCLK 33 51 17 Y2 A2 3 BCLK C RIN1 8 RIN1 TST 32 TST R8 51 18 Y1 A1 2 SDTI C 9 NC BCLK 31 10 R9 LIN2 10 LIN2 SDTI 30 51 C1 47u 1 2 C2 0.1u 20 GND G2 19 R10 51 RIN2 11 RIN2 SDTO 29 SDTO 12 NC NC 28 13 NC VCOM DGND AGND VREF NC 27 NC NC NC NC NC 14 15 16 17 18 19 20 21 22 23 24 25 26 NC VD B VA VT VT C6 2.2u + C7 0.1u C3 0.1u + C4 0.1u + C5 0.1u 1 2 D2V 1 L2 2 JP5 VT L 3 VA C8 10u R12 10 C9 10u C10 10u C11 47u + 1 10u L3 1 A 2 C13 47u + (short) 2 A B C D + VCC G1 1 L1 10u D2V 74LVC541 D5V B D1 1S1588 R11 10k 1 U3A 2 3 U3B 4 PDN H SW1 PDN C12 0.1u 74HC14 74HC14 + A Title Size Document Number AKD4562 AK4562 Sheet E Rev A3 Date: A 1 of Tuesday, June 13, 2000 3 A B C D E D5V PORT1 5 6 5 6 IN VCC IF GND 4 3 2 1 D5V E D5V DIT R13 1k C14 0.1u E R14 10k 2 R15 10k R16 10k D2 1S1588 1 R17 10k 5 U3C 74HC14 6 9 U3D 74HC14 8 R18 51 C16 0.1u C15 10u + U4 1 2 3 4 5 6 7 8 9 10 11 12 MCKO TX DVDD DVSS MCKI BICK SDTI LRCK PDN CSN SCL/CCLK SDA/CDTI DZF NC AVDD AVSS VCOM AOUTL AOUTR CAD0 CAD1 I2C TTL TST 24 23 22 21 20 19 18 17 16 15 14 13 R19 5.1 CSN1 D5V R20 51 CCLK C18 0.1u C19 + 10u + C21 10u PORT2 10 9 8 7 6 1 2 3 4 5 3 1 L H SW2 DIT C17 0.1u CSN CCLK / SCK CDTI / SSI 2 R21 51 CDTI CTRL D D SDTO1 C20 0.1u for 74HCU04, 74HC14, 74HC4040 1 R22 51 R23 51 AK4353 CDTI CCLK U5 10 11 CLK RST Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 9 7 6 5 3 2 4 13 12 14 15 1 L4 10u D5V 2 C23 0.1u 64fs JP6 X_BCLK X_BCLK 32fs C24 0.1u C25 0.1u + C22 47u X_LRCK DIR_LRCK ADC DIR JP7 LRCK R24 51 CSN1 C X_BCLK DIR_BCLK ADC DIR JP8 BCLK fs X_LRCK C SDTO1 D5V 74HC4040 R25 1k D2V BCLK LRCK MCLK BCLK LRCK SDTI ROM PORT3 1 2 3 4 5 10 9 8 7 6 SDTO JP9 SDTO ADC C26 0.1u for SN74LVC07A JP11 SDTI 2 D5V M0/2 U3E 74HC14 M1 SDTO R27 47k 10 11 ROM R26 10k D5V U6A SN74LVC07A 1 JP10 short = "H" MODE open = "L" DIR D5V B SDTI JP12 DIR R28 1k D5V 1 B GND VD 1 LED1 2 R29 1k 12 U3F 74HC14 13 MCLK X1 2 1 VERF 1 L5 2 JP13 CLK DIR EXT XTL 11.2896MHz R30 1M U8A 3 2 1 10u L6 47u 1 LED2 PREM 2 6 5 6 5 GND VCC GND OUT 4 3 2 1 2 PORT4 R31 1k U7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 C Cd/F1 Cc/F0 Cb/E2 Ca/E1 C0/E0 VD+ DGND RXP RXN FSYNC SCK CS12/FCK U VERF Ce/F2 SDATA ERF M1 M0 VA+ AGND FILT MCK M2 M3 SEL CBL 28 27 26 25 24 23 22 21 20 19 18 17 16 15 + C27 10u 4 U8B 74HCU04 JP14 XTE DIR A C31 0.1u + C32 10u M1 C28 0.1u 74HCU04 C29 (open) C30 (open) C33 0.01u C35 0.1u C36 0.01u DIR_LRCK DIR_BCLK R32 1k C34 47n 6 A U8C 5 J1 EXT Title 74HCU04 R33 51 M0/2 CS8412 AKD4562 Document Number Size A3 Date: C D Interface Sheet E Rev A 2 of Monday, January 24, 2000 3 A B A B C D E E + R34 220 E LIN1 LIN2 LIN2 OPGAL OPGL LOUT1 + RIN1 RIN1 RIN2 RIN2 ROUT1 ROUT1 OPGAR OPGR R42 220 J6 LOUT2 8 10 C39 1u R35 10k JP16 LIO LOUT1 J2 LIN C38 10u + JP15 LIN1 LOUT1 C37 22u J3 LOUT1 R36 560 LIN + C40 1u J4 RIN D C41 10u + JP18 OPGL R37 560 JP17 OPGL + R38 560 RIN R39 220 ROUT1 D C43 1u C42 22u R40 10k JP19 RIO C44 1u C OPGR + LOUT2 C45 22u R43 10k + U8D 74HCU04 9 4 B U8E 74HCU04 11 8 ROUT2 C46 22u R45 10k + R44 220 J7 ROUT2 12 U8F 74HCU04 13 12 A A B C + J5 ROUT1 JP20 OPGR R41 560 C U6B SN74LVC07A 3 5 U6C SN74LVC07A 6 U6D SN74LVC07A 9 11 U6E SN74LVC07A 10 B U6F SN74LVC07A 13 A Title Size Document Number AKD4562 Input/Output Sheet E Rev A3 Date: D A 3 of Tuesday, December 21, 1999 3 IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: a. A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. |
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